Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. A typical flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
Each memory cell can be programmed as a single bit per cell (i.e., single level cell—SLC) or multiple bits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage (Vt) determines the data that is stored in the cell. For example, in a single bit per cell, a Vt of 0.5V can indicate a programmed cell while a Vt of −0.5V might indicate an erased cell. The multilevel cell may have multiple Vt ranges that each indicates a different state. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage distribution for the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
FIG. 1 illustrates a typical prior art Vt distribution where the vertical axis is the quantity of cells and the horizontal axis is the threshold voltage Vt. L0 101 is typically referred to as the erased state and has a negative voltage. The remaining positive states are labeled L1 102, L2 103, and L3 104 and are programmed from the erased state 101.
As illustrated in FIG. 2, conventional MLC programming uses incrementally increasing (e.g., ΔV) programming pulses 201 that are applied to the access lines (e.g., word lines) of the memory cell array to achieve discrete levels of Vt for the cells in the array. Between each program pulse, a verify 203 is performed to determine if the cell's target Vt has been achieved. Memory cells that have reached their target Vt are inhibited from further programming during subsequent pulses by biasing of the data line (e.g., bit line).
The variations in each Vt distribution width 110 is an important parameter to control. The tightest possible distribution is desired, as shown in FIG. 1, in order to produce greater spacing 115 between each of the states. This enables easier discrimination between states since the possibility of a higher voltage of one distribution overlapping a lower Vt of the next distribution is reduced. A smaller programming voltage step (ΔV) produces a tighter distribution. However, the smaller programming voltage steps require a longer programming time. Thus, there is a trade-off between tighter distributions and programming speed.
Floating gate-to-floating gate capacitive coupling also affects distribution width. This coupling effect results from increasing density of a memory device by decreasing the distance between memory cells on the memory die. The decreased distance between cells increases the ability of each cell to affect the Vt distribution of adjacent cells.
Program disturb is yet another phenomenon that can affect the Vt distribution size. As mentioned earlier, memory cells that have achieved their target Vt are inhibited from further programming. However, additional programming pulses having high programming voltages necessary for further programming of higher states can still increase the threshold voltages of already programmed memory cells. The increased threshold voltages result in wider threshold distributions.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce Vt distribution width and program disturb without impacting the programming throughput of the memory device.